/**
 @file sys_usw_dma.h

 @date 2012-3-10

 @version v2.0

*/

#ifndef _SYS_USW_DMA_H
#define _SYS_USW_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/****************************************************************
 *
 * Header Files
 *
 ***************************************************************/
/* commone */
#include "sal.h"
#include "ctc_const.h"
#include "ctc_linklist.h"
#include "ctc_debug.h"
#include "ctc_error.h"
#include "ctc_learning_aging.h"
#include "ctc_dma.h"
#include "ctc_packet.h"
#include "drv_api.h"
#include "usw/include/drv_common.h"
/****************************************************************
*
* Functions
*
****************************************************************/
#define SYS_DMA_MTU  (CTC_PKT_MTU + SYS_USW_PKT_HEADER_LEN)

#define SYS_DMA_TX_PKT_MEM_NUM 1024
#define SYS_DMA_TX_PKT_MEM_SIZE (1576)
#define SYS_DMA_TX_MEM_BLOCK_SIZE    16

#define SYS_DMA_HIGH_WEIRGH  8
#define SYS_DMA_MID_WEIGHT 6
#define SYS_DMA_LOW_WEIGHT 4

#define SYS_DMA_PACKET_TX_CHAN_NUM  DRV_ENUM(DRV_DMA_PACKET_TX_CHAN_NUM)
#define SYS_DMA_PACKET_RX_CHAN_NUM  DRV_ENUM(DRV_DMA_PACKET_RX_CHAN_NUM)
#define SYS_DMA_PACKET_RX0_CHAN_ID  DRV_ENUM(DRV_DMA_PACKET_RX0_CHAN_ID)
#define SYS_DMA_PACKET_RX1_CHAN_ID  DRV_ENUM(DRV_DMA_PACKET_RX1_CHAN_ID)
#define SYS_DMA_PACKET_RX2_CHAN_ID  DRV_ENUM(DRV_DMA_PACKET_RX2_CHAN_ID)
#define SYS_DMA_PACKET_RX3_CHAN_ID  DRV_ENUM(DRV_DMA_PACKET_RX3_CHAN_ID)
#define SYS_DMA_PACKET_RX4_CHAN_ID  DRV_ENUM(DRV_DMA_PACKET_RX4_CHAN_ID)
#define SYS_DMA_PACKET_RX5_CHAN_ID  DRV_ENUM(DRV_DMA_PACKET_RX5_CHAN_ID)
#define SYS_DMA_PACKET_RX6_CHAN_ID  DRV_ENUM(DRV_DMA_PACKET_RX6_CHAN_ID)
#define SYS_DMA_PACKET_RX7_CHAN_ID  DRV_ENUM(DRV_DMA_PACKET_RX7_CHAN_ID)
#define SYS_DMA_PACKET_TX0_CHAN_ID  DRV_ENUM(DRV_DMA_PACKET_TX0_CHAN_ID)
#define SYS_DMA_PACKET_TX1_CHAN_ID  DRV_ENUM(DRV_DMA_PACKET_TX1_CHAN_ID)
#define SYS_DMA_PACKET_TX2_CHAN_ID  DRV_ENUM(DRV_DMA_PACKET_TX2_CHAN_ID)
#define SYS_DMA_PACKET_TX3_CHAN_ID  DRV_ENUM(DRV_DMA_PACKET_TX3_CHAN_ID)
#define SYS_DMA_TBL_WR_CHAN_ID      DRV_ENUM(DRV_DMA_TBL_WR_CHAN_ID)
#define SYS_DMA_TBL_WR1_CHAN_ID     DRV_ENUM(DRV_DMA_TBL_WR1_CHAN_ID)
#define SYS_DMA_TBL_RD_CHAN_ID      DRV_ENUM(DRV_DMA_TBL_RD_CHAN_ID)
#define SYS_DMA_PORT_STATS_CHAN_ID  DRV_ENUM(DRV_DMA_PORT_STATS_CHAN_ID)
#define SYS_DMA_FLOW_STATS_CHAN_ID  DRV_ENUM(DRV_DMA_FLOW_STATS_CHAN_ID)
#define SYS_DMA_REG_MAX_CHAN_ID     DRV_ENUM(DRV_DMA_REG_MAX_CHAN_ID)
#define SYS_DMA_REG_BUF_SCAN_CHAN_ID     DRV_ENUM(DRV_DMA_BUF_SCAN_CHAN_ID) /*from AT used for monitor buffer scan*/
#define SYS_DMA_TBL_RD1_CHAN_ID     DRV_ENUM(DRV_DMA_TBL_RD1_CHAN_ID)
#define SYS_DMA_TBL_RD2_CHAN_ID     DRV_ENUM(DRV_DMA_TBL_RD2_CHAN_ID)
#define SYS_DMA_LEARNING_CHAN_ID    DRV_ENUM(DRV_DMA_LEARNING_CHAN_ID)
#define SYS_DMA_HASHKEY_CHAN_ID     DRV_ENUM(DRV_DMA_HASHKEY_CHAN_ID)
#define SYS_DMA_IPFIX_CHAN_ID       DRV_ENUM(DRV_DMA_IPFIX_CHAN_ID)
#define SYS_DMA_BUFFER_CHAN_ID      DRV_ENUM(DRV_DMA_BUFFER_CHAN_ID)
#define SYS_DMA_LATENCY_CHAN_ID     DRV_ENUM(DRV_DMA_LATENCY_CHAN_ID)
#define SYS_DMA_EFD_CHAN_ID         DRV_ENUM(DRV_DMA_EFD_CHAN_ID)
#define SYS_DMA_OAM_CHAN_ID         DRV_ENUM(DRV_DMA_OAM_CHAN_ID)
#define SYS_DMA_SC_OAM_CHAN_ID      DRV_ENUM(DRV_DMA_SC_OAM_CHAN_ID)
#define SYS_DMA_TCAM_SCAN_CHAN_ID   DRV_ENUM(DRV_DMA_TCAM_SCAN_CHAN_ID)
#define SYS_DMA_BATCH_CHAN_ID   DRV_ENUM(DRV_DMA_BATCH_CHAN_ID)
/* unused for tmm start */
#define SYS_DMA_SDC_CHAN_ID         DRV_ENUM(DRV_DMA_SDC_CHAN_ID)
#define SYS_DMA_MONITOR_CHAN_ID     DRV_ENUM(DRV_DMA_MONITOR_CHAN_ID)
/* unused for tmm end */

#define SYS_DMA_TCAM_SCAN_BYTE_PER_UNIT 16
#define SYS_DMA_TCAM_SCAN_ENTRY_PER_UNIT 8
#define SYS_TCAM_SCAN_BMP_OFFSET 14
#define SYS_DMA_PKT_TX_TIMER_CHAN_ID DRV_ENUM(DRV_DMA_PKT_TX_TIMER_CHAN_ID)
/* add for TsingMa.MX */
#define SYS_DMA_FLEXE_RX_RING        DRV_ENUM(DRV_DMA_PACKET_RX7_CHAN_ID)
#define SYS_DMA_FLEXE_TX_RING        DRV_ENUM(DRV_DMA_PACKET_TX2_CHAN_ID)

#define SYS_DMA_RX_CHAN_NUM         4

/* word-len of DMA interrupt vector, refer to DmaCtlIntrFunc_t */
#define SYS_DMA_INTR_VEC 2

#define SYS_USW_DMA_MIN_DATA_POOL_ID 1

#define SYS_USW_DMA_CHAN_POOL_SIZE 256

/*desc not invalid, not need to process, data size set to 1*/
#define SYS_DMA_DESC_NOT_PROC_SIZE  1

/*max dma channel desc num*/
#define SYS_DMA_MAX_PACKET_RX_DESC_NUM (5*1024)
#define SYS_DMA_MAX_PACKET_TX_DESC_NUM (1*1024)
#define SYS_DMA_MAX_LEARNING_DESC_NUM (1*1024)
#define SYS_DMA_MAX_IPFIX_DESC_NUM (1*256)
#define SYS_DMA_MAX_SDC_DESC_NUM (1*256)
#define SYS_DMA_MAX_MONITOR_DESC_NUM (1*256)
#define SYS_DMA_MAX_HASHDUMP_DESC_NUM (1*256)
#define SYS_DMA_MAX_STATS_DESC_NUM (1*256)
#define SYS_DMA_MAX_TAB_RD_DESC_NUM (1*256)
#define SYS_DMA_MAX_TAB_WR_DESC_NUM (1*256)

#define SYS_DMA_EXPORT_IPFIX_MIN_INTERVAL 100

#if (SDB_MEM_MODEL == SDB_MODE)
#define SYS_DMA_INIT_CHECK(lchip) return CTC_E_NONE
#else
#define SYS_DMA_INIT_CHECK(lchip) \
    do { \
        LCHIP_CHECK(lchip);\
        if (NULL == p_usw_dma_master[lchip] || !p_usw_dma_master[lchip]->init){ \
            return CTC_E_NOT_INIT; } \
    } while (0)
#endif

#define COMBINE_64BITS_DATA(high, low, data) \
    {  \
        (data) = high; \
        (data) = (data <<32) | low; \
    }

#if (HOST_IS_LE == 1)
struct sys_dma_batch_cmd_s
{
    uint32 ReqInfo : 16;
    uint32 DataLen : 8;
    uint32 Status : 4;
    uint32 OpCode : 4;
    uint32 Address;
    char data[0];
};
#else
struct sys_dma_batch_cmd_s
{
    uint32 OpCode : 4;
    uint32 Status : 4;
    uint32 DataLen : 8;
    uint32 ReqInfo : 16;
    uint32 Address;
    char data[0];
};
#endif
typedef struct sys_dma_batch_cmd_s sys_dma_batch_cmd_t;

#define DMA_BATCH_HDR_CMD_LEN 8
#define DMA_BATCH_OP_CODE_SIGLE_WRITE 0
#define DMA_BATCH_OP_CODE_SIGLE_READ 1
#define DMA_BATCH_OP_CODE_BURST_WRITE 2
#define DMA_BATCH_OP_CODE_BURST_READ 3
#define DMA_BATCH_OP_CODE_MASK_WRITE 4

#define DMA_BATCH_ENCODE_CMD_REQ_INFO(CORE_BMP, PP_BMP, DP_BMP) (((CORE_BMP) << 10) | ((PP_BMP) << 2) | ((DP_BMP) & 0x3))
#define SYS_DMA_ALLOC(lchip,size,type)      g_dal_op.dma_alloc(SYS_MAP_LDEV(lchip),size,type)
#define SYS_DMA_FREE(lchip,ptr)             g_dal_op.dma_free(SYS_MAP_LDEV(lchip),ptr)

#define SYS_DMA_LOGIC_TO_PHY(lchip,laddr)   ((g_dal_op.logic_to_phy != NULL) ? g_dal_op.logic_to_phy(SYS_MAP_LDEV(lchip),laddr):\
            (p_usw_dma_master[lchip]->phy_base + ((uintptr)(laddr) - (uintptr)(p_usw_dma_master[lchip]->p_virt_base))))

#define SYS_DMA_PHY_TO_LOGIC(lchip,paddr)   ((g_dal_op.phy_to_logic != NULL) ? g_dal_op.phy_to_logic(SYS_MAP_LDEV(lchip),paddr) :\
            (void*)((char*)(p_usw_dma_master[lchip]->p_virt_base) + (paddr - p_usw_dma_master[lchip]->phy_base)))

/* Notice: Only can be used in sys_usw_dma.c init process, these macros have performance limit!! Cannot used in function process */
#if (HOST_IS_LE == 1 && SDK_WORK_PLATFORM == 0 && defined DUET2)
#define GetDsDescEncap2(X, ...)  DRV_GET_FLD(X, DsDescLittle, ##__VA_ARGS__)
#define SetDsDescEncap2(X, ...)\
do{\
    if (DRV_IS_DUET2(lchip))  \
    {\
        DRV_SET_FLD(X, DsDescLittle, ##__VA_ARGS__);\
    }\
    else\
    {\
        DRV_SET_FLD(X, DsDesc, ##__VA_ARGS__);\
    }\
}while(0)
#else
#define GetDsDescEncap2(X, ...) DRV_GET_FLD(X, DsDesc, ##__VA_ARGS__)
#define SetDsDescEncap2(X, ...) DRV_SET_FLD(X, DsDesc, ##__VA_ARGS__)
#endif


#define GetDsDescEncap(X, ...)   DRV_GET_FLD(X, DsDesc, ##__VA_ARGS__)
#define SetDsDescEncap(X, ...)   DRV_SET_FLD(X, DsDesc, ##__VA_ARGS__)

#ifdef DMA_CACHE_COHERENCE_EN
#define SYS_USW_DMA_CACHE_FLUSH(lchip, addr, size)\
do{\
        g_dal_op.dma_cache_flush(SYS_MAP_LDEV(lchip), SYS_DMA_LOGIC_TO_PHY(lchip, (void*)addr), size);\
}while(0)

#define SYS_USW_DMA_CACHE_INVALID(lchip, addr, size)\
do{\
        g_dal_op.dma_cache_inval(SYS_MAP_LDEV(lchip), SYS_DMA_LOGIC_TO_PHY(lchip, (void*)addr), size);\
}while(0)

#define SYS_USW_DMA_CACHE_INVALID_WITH_PHY_ADDR(lchip, phy_addr, size)\
do{\
        g_dal_op.dma_cache_inval(SYS_MAP_LDEV(lchip), phy_addr, size);\
}while(0)

#define SYS_USW_DMA_CACHE_FLUSH_WITH_PHY_ADDR(lchip, phy_addr, size)\
do{\
        g_dal_op.dma_cache_flush(SYS_MAP_LDEV(lchip), phy_addr, size);\
}while(0)
#else
#define SYS_USW_DMA_CACHE_FLUSH(lchip, addr, size)
#define SYS_USW_DMA_CACHE_INVALID(lchip, addr, size)
#define SYS_USW_DMA_CACHE_INVALID_WITH_PHY_ADDR(lchip, phy_addr, size) 
#define SYS_USW_DMA_CACHE_FLUSH_WITH_PHY_ADDR(lchip, phy_addr, size) 
#endif

/* write DmaCtlTab_t to recycle desciptors, for uml, write desc-depth */
#if (0 == SDK_WORK_PLATFORM)
#define SYS_USW_DMA_CLEAR_MULTI_DESC_WITH_IO(lchip, p_dma_chan, cnt) \
do{\
    uint32 vld_num = cnt;\
    uint32 cmd = 0;\
    SYS_USW_DMA_CACHE_FLUSH(lchip, p_dma_chan->p_desc, sizeof(sys_dma_desc_t)*p_dma_chan->desc_depth);\
    cmd = DRV_IOW(DmaCtlTab_t, DRV_ENTRY_FLAG);\
    DRV_IOCTL(lchip, p_dma_chan->channel_id, DRV_CMD_PP_EN(cmd), &vld_num);\
}while(0)
#else
#define SYS_USW_DMA_CLEAR_MULTI_DESC_WITH_IO(lchip, p_dma_chan, cnt) \
do{\
    uint32 vld_num = p_dma_chan->desc_depth;\
    uint32 cmd = 0;\
    SYS_USW_DMA_CACHE_FLUSH(lchip, p_dma_chan->p_desc, sizeof(sys_dma_desc_t)*p_dma_chan->desc_depth);\
    cmd = DRV_IOW(DmaCtlTab_t, DRV_ENTRY_FLAG);\
    DRV_IOCTL(lchip, p_dma_chan->channel_id, DRV_CMD_PP_EN(cmd), &vld_num);\
}while(0)
#endif

/* reset mask to enable interrupt, for uml, just set mask to 0 */
#if (0 == SDK_WORK_PLATFORM)
#define SYS_USW_DMA_INTR_ENABLE(lchip, tbl_id, ds, chan) \
do{\
    uint32 cmd = 0;\
    CTC_BIT_SET(((uint32*)ds)[0], chan);\
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);\
    DRV_IOCTL(lchip, INTR_INDEX_MASK_RESET, DRV_CMD_PP_EN(cmd), &ds);\
}while(0)
#else
#define SYS_USW_DMA_INTR_ENABLE(lchip, tbl_id, ds, chan) \
do{\
    uint32 cmd = 0;\
    CTC_BIT_UNSET(((uint32*)ds)[0], chan);\
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);\
    DRV_IOCTL(lchip, INTR_INDEX_MASK_SET, DRV_CMD_PP_EN(cmd), &ds);\
}while(0)
#endif


/**
 @brief dma desc define, for 4-bytes align
*/
struct sys_dma_desc_s
{
    DsDesc_m desc_info;
};
typedef struct sys_dma_desc_s sys_dma_desc_t;
struct sys_dma_desc_info_s
{
    uint16   value0;  /* for stats dma means mac id ,
                         for info dma means current entry index in desc,
                         for tcam scan dma means mem_id and sub id,
                         for buffer scan dma chan, value0[4:1] means pp_id, value0[0] means dp_id
                         other dma function have no meaning */
    uint16   value1;  /*used to record desc real size, for tcam scan means entry size, for buffer scan dma chan, means tbl_id*/
    void*   data_addr; /* used to record desc data memory logic address, no need read phy address 
                          from desc and convert to logic address, for stats dma, info dma, tcam scan, pkt rx */
};
typedef struct sys_dma_desc_info_s sys_dma_desc_info_t;
struct sys_dma_desc_ts_s
{
    uint32 ts_ns[2];
};
typedef struct sys_dma_desc_ts_s sys_dma_desc_ts_t;

/**
 @brief dma learning info struct define, for 4-bytes align
*/
struct sys_dma_learning_info_s
{
    DmaFibLearnFifo_m learn_info;
    uint32 learn_pad[3];
};
typedef struct sys_dma_learning_info_s sys_dma_learning_info_t;

enum sys_dma_info_type_e
{
    SYS_DMA_INFO_TYPE_LEARN,
    SYS_DMA_INFO_TYPE_HASHDUMP,
    SYS_DMA_INFO_TYPE_IPFIX,
    SYS_DMA_INFO_TYPE_SDC,
    SYS_DMA_INFO_TYPE_MONITOR,

    SYS_DMA_INFO_TYPE_MAX
};
typedef  enum sys_dma_info_type_e sys_dma_info_type_t;

enum sys_dma_cb_type_e
{
    SYS_DMA_CB_TYPE_LERNING,
    SYS_DMA_CB_TYPE_IPFIX,
    SYS_DMA_CB_TYPE_MONITOR,
    SYS_DMA_CB_TYPE_PORT_STATS,
    SYS_DMA_CB_TYPE_FLOW_STATS,
    SYS_DMA_CB_TYPE_SDC_STATS,
    SYS_DMA_CB_TYPE_DOT1AE_STATS,
    SYS_DMA_CB_TYPE_OAM,/*__TODO__*/
    SYS_DMA_CB_TYPE_SCOAM_EVENT,/*__TODO__*/
    SYS_DMA_CB_TYPE_NPM_STATS,
    SYS_DMA_CB_TYPE_BUFFER_MON,
    SYS_DMA_CB_TYPE_LATENCY_MON,
    SYS_DMA_CB_TYPE_EFD_MON,
    SYS_DMA_CB_TYPE_BUFFER_MON_SCAN,
    SYS_DMA_CB_TYPE_FLOW_STATS_RAM_STATUS,
    SYS_DMA_CB_MAX_TYPE
};
typedef  enum sys_dma_cb_type_e sys_dma_cb_type_t;

enum sys_dma_func_type_e
{
    SYS_DMA_FUNC_PACKET_RX,      /* DMA Packet Rx Function */
    SYS_DMA_FUNC_PACKET_TX,      /* DMA Packet Tx Function */
    SYS_DMA_FUNC_TABLE_R,        /* DMA Table Read Function */
    SYS_DMA_FUNC_TABLE_W,        /* DMA Table Write Function */
    SYS_DMA_FUNC_STATS,          /* DMA Stats Function */
    SYS_DMA_FUNC_HW_LEARNING,    /* DMA Learning Function, software leaning */
    SYS_DMA_FUNC_IPFIX,          /* DMA Ipfix Function */
    SYS_DMA_FUNC_SDC,            /* DMA SDC Function */
    SYS_DMA_FUNC_MONITOR,        /* DMA Monitor Function */
    SYS_DMA_FUNC_BUFFER_MON,     /* DMA Buffer Monitor Function */
    SYS_DMA_FUNC_LATENCY_MON,    /* DMA Latency Monitor Function */
    SYS_DMA_FUNC_EFD_MON,        /* DMA EFD/DLB Monitor Function */
    SYS_DMA_FUNC_TIMER_PACKET,   /* DMA packet tx on timer */
    SYS_DMA_FUNC_OAM,            /* DMA OAM Function */
    SYS_DMA_FUNC_SC_OAM,         /* DMA SC OAM Function */
    SYS_DMA_FUNC_TCAM_SCAN,      /* DMA Tcam Scan Function */
    SYS_DMA_FUNC_BATCH,          /* DMA Batch Function */

    SYS_DMA_FUNC_MAX
};
typedef enum sys_dma_func_type_e sys_dma_func_type_t;

struct sys_dma_info_s
{
    void* p_data;
    uint32 entry_num; /*uint32 for chip agent*/
    uint32  seconds;
    uint32  nanoseconds;
    uint8   base_lchip; /*for AT core 1*/
    uint8   rsv[3];
};
typedef struct sys_dma_info_s sys_dma_info_t;

struct sys_dma_npm_data_s
{
    uint8  type;
    uint8  rsv[7];
    uint64 time_stamp;
};
typedef struct sys_dma_npm_data_s sys_dma_npm_data_t;

struct sys_dma_reg_s
{
    void* p_data;
    void* p_ext;  /*for port stats means mac_id,for flow stats means block id*/
};
typedef struct sys_dma_reg_s sys_dma_reg_t;

typedef int32 (* DMA_CB_FUN_P)  (uint8 lchip, void* p_data);
struct dma_dump_cb_parameter_s
{
    uint32 entry_count;
    uint16 threshold;
    uint8  fifo_full;
    uint8  rsv;
};
typedef struct dma_dump_cb_parameter_s dma_dump_cb_parameter_t;
typedef int32 (*DMA_DUMP_FUN_P)(uint8 lchip, dma_dump_cb_parameter_t* parameter, uint16* p_entry_num, void* p_data);

#define SYS_USW_DMA_ENCODE_OP_BMP2(lchip, is_read, core_bmp, pp_bmp, dp_bmp) _sys_usw_dma_encode_table_op_bmp2(lchip, is_read, core_bmp, pp_bmp, dp_bmp)
#define SYS_USW_DMA_ENCODE_OP_BMP(lchip, level, pp_id, dp_id) _sys_usw_dma_encode_table_op_bmp(lchip, level, pp_id, dp_id)
struct sys_dma_tbl_rw_s
{
    uint32* buffer;
    uint32  tbl_addr;

    uint32  entry_num;
    uint32  entry_len;

    uint32  is_pause:1;
    uint32  user_dma_mode:2; /*use the user alloced dma memory*/
    uint32  entry_offset:16;
    uint32  desc_index:13;

    uint32 time_stamp[2];
    uint16 op_bmp; /*refer to SYS_USW_DMA_ENCODE_OP_BMP2 or SYS_USW_DMA_ENCODE_OP_BMP*/
    uint8  copy_mode; /*only for write*/

};
typedef struct sys_dma_tbl_rw_s sys_dma_tbl_rw_t;

#define SYS_DMA_REPORT_TYPE_IPFIX_IGS_START 0 /*ctc_ipfix_export_reason_t*/
#define SYS_DMA_REPORT_TYPE_IPFIX_IGS_END 15
#define SYS_DMA_REPORT_TYPE_IPFIX_EGS_START 16 /*ctc_ipfix_export_reason_t*/
#define SYS_DMA_REPORT_TYPE_IPFIX_EGS_END 31
#define SYS_DMA_REPORT_TYPE_IRM0 MCHIP_CAP(SYS_CAP_DMA_REPORT_TYPE_IRM0)
#define SYS_DMA_REPORT_TYPE_IRM1 MCHIP_CAP(SYS_CAP_DMA_REPORT_TYPE_IRM1)
#define SYS_DMA_REPORT_TYPE_ERM_STATS MCHIP_CAP(SYS_CAP_DMA_REPORT_TYPE_ERM_STATS)
#define SYS_DMA_REPORT_TYPE_ERM_EVENT MCHIP_CAP(SYS_CAP_DMA_REPORT_TYPE_ERM_EVENT)
#define SYS_DMA_REPORT_TYPE_LATENCY_STATS MCHIP_CAP(SYS_CAP_DMA_REPORT_TYPE_LATENCY_STATS)
#define SYS_DMA_REPORT_TYPE_LATENCY_EVENT MCHIP_CAP(SYS_CAP_DMA_REPORT_TYPE_LATENCY_EVENT)
#define SYS_DMA_REPORT_TYPE_EFD MCHIP_CAP(SYS_CAP_DMA_REPORT_TYPE_EFD)
#define SYS_DMA_REPORT_TYPE_DLB MCHIP_CAP(SYS_CAP_DMA_REPORT_TYPE_DLB)
#define SYS_DMA_REPORT_TYPE_OAM MCHIP_CAP(SYS_CAP_DMA_REPORT_TYPE_OAM)
#define SYS_DMA_REPORT_TYPE_SPNOAM_LOCAL MCHIP_CAP(SYS_CAP_DMA_REPORT_TYPE_SPNOAM_LOCAL)
#define SYS_DMA_REPORT_TYPE_SPNOAM_MASTER MCHIP_CAP(SYS_CAP_DMA_REPORT_TYPE_SPNOAM_MASTER)
#define SYS_DMA_REPORT_TYPE_LEARNING MCHIP_CAP(SYS_CAP_DMA_REPORT_TYPE_LEARNING)
#define SYS_DMA_REPORT_TYPE_AGING MCHIP_CAP(SYS_CAP_DMA_REPORT_TYPE_AGING)
#define SYS_DMA_REPORT_TYPE_FDB_DUMP MCHIP_CAP(SYS_CAP_DMA_REPORT_TYPE_FDB_DUMP)
#define SYS_DMA_REPORT_TYPE_MAX 48


/* do not include ssx info */
#define SYS_DMA_INFO_MAX_SUB_TYPE SYS_DMA_REPORT_TYPE_MAX

typedef enum sys_usw_dma_export_dest_type_e
{
    SYS_DMA_EXP_DEST_TYPE_CPU = 0,
    SYS_DMA_EXP_DEST_TYPE_EUNIT,
    SYS_DMA_EXP_DEST_TYPE_DMA_EXP,
    SYS_DMA_EXP_DEST_TYPE_EUNIT1, /*AT add*/

    SYS_DMA_EXP_DEST_TYPE_MAX
}sys_usw_dma_export_dest_type_t;

typedef struct sys_usw_dma_export_map_s
{
    uint8 type;         /*[in] SYS_DMA_REPORT_TYPE_XXX */
    uint8 dest_bmp;     /*[in] bit0:HCPU; bit1:ECPU; bit2: Encap; AT: bit3->ECPUDMA1; sys_usw_dma_export_dest_type_t*/
    uint8 rsv[2];

    uint8 ring_id;      /*[out] host cpu ring id*/
    uint8 fifo_id;      /*[out] dma export fifo id*/
    uint8 eunit_ring_id;/*[out] eunit ring id*/
    uint8 eunit1_ring_id;/*[out] AT, ecpuDMA1*/
}sys_usw_dma_export_map_t;

typedef struct sys_usw_dma_export_pkt_cfg_s
{
    uint8 fifo_id;                  /**< 0~3 */
    uint8 rsv[3];
    uint32 nhid;                    /**< export destination */
    uint32 metadata[3];             /**< user defined metadata */
    uint32 end_tlv;                 /**< user defined end tlv */
    uint64 interval;
}sys_usw_dma_export_pkt_cfg_t;

typedef struct sys_dma_sync_tbl_s
{
    uint32  pp_id : 3;
    uint32  dp_id : 1;
    uint32  first_sync : 1; /*means first sync at first scan interval*/
    uint32  rsv : 27;
    uint32 tbl_id;
    uint32 ts[2]; /*timestamp from description*/
}sys_dma_sync_tbl_t;

struct sys_dma_batch_op_s
{
    uint8   op; /*0: read; 1: write*/
    uint8   sigle; /*not enable burst r/w*/
    uint8   core_bmp;
    uint16 pp_bmp;
    uint8   dp_bmp;
    uint8   error;
    uint16  entry_num;
    uint16  entry_sz;
    uint16  entry_offset;
    uint32  addr;
    uint8*   write_data; /*per byte data*/
	uint8*   write_mask; /*per byte mask*/
    uint32  status[2];
};
typedef struct sys_dma_batch_op_s sys_dma_batch_op_t;


#define GET_CHAN_TYPE(chan_id) p_usw_dma_master[lchip]->chan_type[chan_id]
#define SYS_DMA_FLOW_STATS_DESC_DEPTH 3

#define SYS_DMA_IO_BMP_CORE 6
#define SYS_DMA_IO_BMP_PP 2

#define SYS_USW_DMA_INFO_OFFSET 12
#define SYS_USW_DMA_GET_INFO_ADDR(lchip, p_cpu_info) (void*)((uint8*)(p_cpu_info) + SYS_USW_DMA_INFO_OFFSET)

extern int32
sys_usw_dma_init(uint8 lchip, ctc_dma_global_cfg_t* dma_global_cfg);

extern int32
sys_usw_dma_init_done(uint8 lchip, uint8 in_chip_reset);

extern void*
sys_usw_dma_tx_alloc(uint8 lchip, uint32 pkt_size);

extern int32
sys_usw_dma_tx_free(uint8 lchip, void* addr);

extern int32
sys_usw_dma_pkt_tx(uint8 lchip, ctc_pkt_tx_t* p_pkt_tx);

extern int32
sys_usw_dma_performance_test(uint8 lchip, ctc_pkt_tx_t* p_pkt_tx);

extern int32
sys_usw_dma_rw_table_user_dma_addr(uint8 lchip, sys_dma_tbl_rw_t* tbl_cfg);

extern int32
sys_usw_dma_show_stats(uint8 lchip);

extern int32
sys_usw_dma_register_cb(uint8 lchip, uint8 type, void* cb);

extern int32
sys_usw_dma_register_rx_cb(uint8 lchip, CTC_PKT_RX_CALLBACK cb);

extern int32
sys_usw_dma_get_dump_cb(uint8 lchip, void**cb, void** user_data);

extern int32
sys_usw_dma_sync_info_func(uint8 lchip, uint8 type, sys_dma_info_t* p_info);

extern int32
sys_usw_dma_clear_chan_data(uint8 lchip, uint8 chan_id);

extern int32
sys_usw_dma_set_chan_en(uint8 lchip, uint8 chan_id, uint8 chan_en);

extern int32
sys_usw_dma_get_chan_en(uint8 lchip, uint8 chan_id, uint8* chan_en);

extern int32
sys_usw_dma_wait_desc_done(uint8 lchip, uint8 chan_id);

extern int32
sys_usw_dma_get_packet_rx_chan(uint8 lchip, uint16* p_num);

extern int32
sys_usw_dma_get_hw_learning_sync(uint8 lchip, uint8* b_sync);

extern int32
sys_usw_dma_set_mac_stats_timer(uint8 lchip, uint32 timer);

extern int32
sys_usw_dma_set_npm_stats_enable(uint8 lchip, bool enable);

extern int32
sys_usw_dma_deinit(uint8 lchip);

extern int32
sys_usw_dma_set_pkt_timer(uint8 lchip, uint32 timer, uint8 enable);

extern int32
sys_usw_dma_set_packet_timer_cfg(uint8 lchip, uint16 max_session, uint16 interval, uint16 pkt_len, uint8 is_destroy);

extern int32
sys_usw_dma_set_session_pkt(uint8 lchip, uint16 session_id, ctc_pkt_tx_t* p_pkt);

extern int32
sys_usw_dma_set_tcam_scan_mode(uint8 lchip, uint8 mode, uint32 timer);

extern int32
sys_usw_dma_export_map(uint8 lchip, sys_usw_dma_export_map_t* p_map);

extern int32
sys_usw_dma_export_pkt_cfg(uint8 lchip, sys_usw_dma_export_pkt_cfg_t* p_cfg);

extern int32
sys_usw_dma_set_cfg_size(uint8 lchip, int32 chan_id, uint32 desc_idx, uint32 enable);

extern int32
sys_usw_dma_get_flow_stats_sync_mode(uint8 lchip);


extern int32
sys_usw_dma_get_dma_memory(uint8 lchip, uint8 type, uint32** p_mem);
extern int32
sys_usw_dma_get_flow_stats_memory(uint8 lchip, uint8 block_id, uint32** p_mem, uint8* p_desc_done);
extern int32
sys_usw_dma_knet_reset_en(uint8 lchip, uint8 reset_en);

extern int32
sys_usw_dma_clear_pkt_stats(uint8 lchip, uint8 para);

extern int32
sys_usw_dma_free_task(uint8 lchip);

extern uint32
_sys_usw_dma_encode_table_op_bmp(uint8 lchip, uint8 tbl_level, uint8 pp_id, uint8 dp_id);
extern uint32
_sys_usw_dma_encode_table_op_bmp2(uint8 lchip, uint8 is_read, uint8 core_bmp, uint16 pp_bmp, uint8 dp_bmp);

extern int32
sys_usw_dma_tx_alloc2(uint8 lchip, ctc_pkt_buf_pool_t* p_pool);

extern int32
sys_usw_dma_tx_free2(uint8 lchip, ctc_pkt_buf_pool_t* p_pool);


#ifdef __cplusplus
}
#endif

#endif

